PCI transaction ordering rules require that all the data arrive in memory before the value may be returned from the register. In order to ensure that all the data has arrived in memory, the interrupt handler must read a register on the device which raised the interrupt. When a device writes data to memory, then raises a pin-based interrupt, it is possible that the interrupt may arrive before all the data has arrived in memory (this becomes more likely with devices behind PCI-PCI bridges). MSIs are never shared, so this problem cannot arise. To support this, the kernel must call each interrupt handler associated with an interrupt, which leads to reduced performance for the system as a whole. Pin-based PCI interrupts are often shared amongst several devices. There are three reasons why using MSIs can give an advantage over traditional pin-based interrupts.
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